SN74LS173 4-Bit D-Type Register with 3-State Outputs
Low-Power Schottky TTL Register for Bus-Oriented Applications
The SN74LS173 is a 4-bit D-type register featuring 3-state outputs and asynchronous master reset. This TTL integrated circuit provides parallel storage for 4 data bits with high-impedance outputs for bus-oriented applications. It operates with a 5V supply and is compatible with 7400 series logic.
4
Bits
15 ns (typical)
Propagation Delay
5V (4.75-5.25V)
Supply Voltage
Key features
4-Bit Parallel Storage
Stores four data bits simultaneously with parallel-in/parallel-out operation.
3-State Outputs
High-impedance outputs allow connection to a common bus without interference.
Asynchronous Clear
Master reset clears all flip-flops independent of the clock.
Positive-Edge Triggered Clock
Data is captured on the rising edge of the clock signal.
Compatible with 74LS Family
Standard TTL logic levels ensure easy integration with existing designs.
Technical specifications
Logic Family
74LS
Number of Bits
4
Input Type
Parallel
Output Type
3-State
Clock Frequency
Up to 35 MHz
Propagation Delay
15 ns (typical)
Supply Voltage
4.75V to 5.25V
Power Consumption
32 mW (typical)
Operating Temperature
0°C to +70°C
Package
16-pin DIP, SOIC
Pinout
Pin
Function
1
CLR – Asynchronous Clear (active LOW)
2
D0 – Data Input Bit 0
3
D1 – Data Input Bit 1
4
D2 – Data Input Bit 2
5
D3 – Data Input Bit 3
6
CLK – Clock Input (positive edge)
7
G1 – Output Enable 1 (active LOW)
8
GND – Ground
9
G2 – Output Enable 2 (active LOW)
10
Q3 – Output Bit 3
11
Q2 – Output Bit 2
12
Q1 – Output Bit 1
13
Q0 – Output Bit 0
14
VCC – +5V Power Supply
Applications
Data buffering for microprocessorsBidirectional bus interfaceCascadable shift registersState storage in logic controllersTemporary data storage in digital systemsBus arbitration and multiplexing
What's in the box
1x SN74LS173N IC (16-pin DIP)
Anti-static protective packaging
Downloads
Datasheet (PDF)
Application Note
Truth Table
Timing Diagram
Use a 0.1µF decoupling capacitor between VCC and GND near the IC. Tie unused inputs to VCC or GND to prevent floating. Observe setup and hold times (20 ns and 5 ns) for reliable clocked operation.
