April 13, 2025 On April 13, 2025

IC 74173 – 4-Bit D-Type Register with 3-State Outputs

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IC 74173 – 4-Bit D-Type Register with 3-State Outputs

TTL Quad D Flip-Flop with Asynchronous Clear and Output Enable

Introduction

The SN74LS173 is a 4-bit D-type register featuring 3-state outputs and asynchronous master reset. This TTL integrated circuit provides parallel storage for 4 data bits with high-impedance outputs for bus-oriented applications.

Key Features

🔢 4-Bit Storage

Parallel-in/parallel-out operation

🚦 3-State Outputs

High-impedance bus interface

🔄 Asynchronous Clear

Master reset independent of clock

⏱️ Clocked Operation

Positive-edge triggered

🔌 Standard TTL

Compatible with 7400 series logic

🏗️ Robust Design

16-pin DIP package

Technical Specifications

Logic Family	74LS (Low-power Schottky)
Number of Bits	4
Input Type	Parallel
Output Type	3-State
Clock Frequency	Up to 35MHz
Propagation Delay	15ns (typical)
Supply Voltage	4.75V to 5.25V
Power Consumption	32mW (typical)
Operating Temperature	0°C to +70°C
Package Type	16-pin DIP, SOIC

Pin Configuration

Pin	Name	Function
1	CLR	Asynchronous Clear (active LOW)
2	D0	Data Input Bit 0
3	D1	Data Input Bit 1
4	D2	Data Input Bit 2
5	D3	Data Input Bit 3
6	CLK	Clock Input (positive edge)
7	G1	Output Enable 1 (active LOW)
8	GND	Ground
9	G2	Output Enable 2 (active LOW)
10	Q3	Output Bit 3
11	Q2	Output Bit 2
12	Q1	Output Bit 1
13	Q0	Output Bit 0
14	VCC	+5V Power Supply

Note: Both G1 and G2 must be LOW to enable outputs

Truth Table

CLR	CLK	G1	G2	Dn	Qn
L	X	X	X	X	L
H	↑	X	X	L	L
H	↑	X	X	H	H
H	H/L	X	X	X	Q0
H	X	H	X	X	Z
H	X	X	H	X	Z

Legend: H=HIGH, L=LOW, X=Don’t Care, ↑=Rising Edge, Z=High Impedance, Q0=Previous State

Typical Application Circuit

Bus Interface Implementation

Connect data inputs to source (microcontroller/other logic)
Connect outputs to common bus with other 3-state devices
Use CLK for synchronous data transfer
Control outputs with G1/G2 enable signals
Reset all flip-flops with CLR when needed

Timing Characteristics

Setup Time (t_su)

20ns (data to clock rise)

Hold Time (t_h)

5ns (data after clock rise)

Clock Pulse Width (t_w)

25ns (minimum)

Propagation Delay (t_pd)

15ns (CLK to Q, typical)

Note: All timing values measured at V_CC=5V, T_A=25°C

Application Examples

💾 Data Buffering

Temporary storage for processors

🔄 Bus Interface

Bidirectional data bus control

🧮 Shift Registers

Cascadable for serial operations

🎮 Control Systems

State storage in logic controllers

Replacement Guide

Part Number	Family	Features
SN74LS173	Low-power Schottky	Original version
SN74HC173	High-speed CMOS	Lower power, wider voltage
SN74F173	Fast TTL	Higher speed (100MHz)
CD40174	CMOS	6-bit version